Various conventional architectures supporting a two-dimensional array of avalanche photodiodes in a photon-counting environment have been proposed. One such conventional architecture is the MOSFET matrix architecture. An example of this architecture is illustrated in FIG. 13.
As illustrated in FIG. 13, the pixels 500 of an array are connected to row lines through MOSFET transistors 510. Each row line is biased above breakdown by bias/sense circuits 505. By applying a charging pulse to the gates of the transistors 510 in a column, the entire column of avalanche photodiodes 500 can be biased above breakdown.
If breakdown is started in a pixel 500, the pixel 500 will be discharged by the breakdown current. This breakdown will quench automatically when the voltage has dropped below the breakdown voltage. If a charge pulse is subsequently applied to the gate of the transistor 510 in a column, the pixel 500 can be recharged.
In this device, if a photon initiated the avalanche breakdown, a large charge will be required to recharge the pixel 500. If no photon has been detected by the pixel 500, no current will flow through the row line of the pixel 500. By continuously scanning the pixel 500 and the surrounding array of pixels, a multitude of 1-bit images can be accumulated and added together to generate an image with many grey-values.
The MOSFET architecture also includes column select circuitry 501 to select the column of pixels to scan or sense and I/O circuitry 507 to gate the image data-from the row lines off the chip. The column select circuitry 501 and the I/O circuitry 507 are controlled by control circuitry 503.
Another conventional architecture supporting two-dimensional arrays of avalanche photodiodes in a photon-counting environment is the diode matrix architecture. An example of this architecture is illustrated in FIG. 14.
As illustrated in FIG. 14, each pixel 600 is connected to a column line through diode 620 and a row line through diode 610. Both lines are biased at a voltage larger than the breakdown voltage of the corresponding diode. If a photon is detected by one of the pixels 600, the breakdown current of the pixel 600 will flow through the column line and row line contacting the pixel 600. The diodes contacting the other pixels prevent the current from flowing into other column lines and row lines.
By detecting the currents through the column lines and the row lines, the position of the incident photons can be determined. After breakdown, quench circuits 630 reduce the voltages at the column and row lines associated with the pixel currently experiencing breakdown.
The diode architecture also includes I/O circuitry 507 to gate the image data from the column and row lines off the chip.
In looking at these conventional architectures, a high timing resolution can be realized by the diode matrix architecture. On the other hand, large photon count rates can be realized by the MOSFET matrix architecture. However, neither of these conventional architectures can realize both a high timing resolution and large photon count rates.
Therefore, it is desirable to realize a read-out architecture that enables a high timing resolution and large photon count rates. Moreover, it is desirable to realize a read-out architecture that enables the realization of real-time digital photon-counting focal-plane-array intensity imagers that are applicable to night vision, remote surveillance, adaptive optics, biodetection, micro air vehicles, satellites, and bio-fluorescence.